In very large scale integration (“VLSI”) designs of integrated circuitry, power consumption is a significant factor. For example, power consumption has a direct impact on battery life, heat dissipation, packaging requirements, and other design criteria for systems that include such integrated circuitry. Generally, a lower power consumption is desirable. Accordingly, previous techniques have been developed for modeling designs of integrated circuitry, including previous techniques for estimating power consumption of such integrated circuitry.
Nevertheless, a need has arisen for a design structure for estimating power consumption of integrated circuitry, in which various shortcomings of previous techniques are overcome. For example, a need has arisen for a design structure for estimating power consumption of integrated circuitry, in which power consumption is estimated with higher efficiency and accuracy.